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 Preliminary programme (version April 11, 2006)
TUESDAY, April 18
| • 16:00 - 20:00 |
Registration
- Masarykova kolej
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WEDNESDAY, April 19  show/hide wednesday
| • 7:30 - 8:30 |
Registration
- Masarykova kolej
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| • 08:30 - 08:50 |
Bernd Straube, Ondřej Novák, Leandro Soares Indrusiak
- DDECS and CCE Welcome
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| • 08:50 - 09:50 |
Ketan Paranjape, Intel Corp.
- Keynote Presentation
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| • 09:50 - 10:20 |
Coffee break
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| • 10:20 - 10:30 |
Matteo Sonza Reorda
- DDECS Opening Remarks
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| • 10:30 - 11:30 |
Session I
- Design Validation
| P.- A. Mudry, G. Zufferey, G. Tempesti |
An Hybrid Genetic Algorithm for Constrained Hardware-Software Partitioning |
| R. Wimmer, M. Herbstritt, B. Becker |
Minimization of Large State Spaces using Symbolic Branching Bisimulation |
| J. Eisinger, I. Polian, B. Becker, A. Metzner, S. Thesing, R. Wilhelm |
Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis |
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| • 11:30 - 11:50 |
Coffee break
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| • 11:50 - 13:10 |
Session II
- Physical and IP Design
| F. Tobajas, R. Esper-Chaín, R. Regidor, O. Santana, R. Sarmiento |
A Low Power 2.5 Gbps 1:32 Deserializer in SiGe BiCMOS Technology |
| K. Granhaug, S. Aunet |
Six Subthreshold Full Adder Cells Characterized in 90 nm CMOS Technology |
| A. Rashid, F. H. P. Fitzek, O. Olsen, M. Gade, Y. Le Moullec |
A Low Complexity, High Speed, Regular and Flexible Reed Solomon Decoder for Wireless Communication |
| Á. Vámos, A. Timár, G. Bognár |
Comprehensive Design of a High Frequency PLL Synthesizer for ZigBee Application |
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| • 13:10 - 14:10 |
Lunch
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| • 14:10 - 15:50 |
Session III
- Innovative Design Techniques
| A. Ngouanga, G. Sassatelli, L. Torres, B. Suarez Andre |
A Contextual Resources use: a Proof of Concept through the APACHES’ Platform |
| Z. Stamenković, C. Wolf, G. Schoof, J. Gaisler |
LEON-2: General Purpose Processor for a Wireless Engine |
| L. Sterpone, M. Violante |
ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications |
| A. Kulmala, E. Salminen, O. Lehtoranta, T. D. Hämäläinen, M. Hännikäinen |
Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder |
| E. Aho, J. Vanne, T. D. Hämäläinen |
Parallel Memory Architecture for Arbitrary Stride Accesses |
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| • 15:50 - 16:50 |
Coffee break+ Poster Session I
| G. Pastuszak |
Architecture Design for the Context Formatter in the H.264/AVC Encoder |
| L. Ručkay |
Recognition of DRM Signal in Frequency Domain and Hardware Demands |
| V.V. Belkin, S.G. Sharshunov |
ISA Based Functional Test Generation with Application to Self-Test of RISC Processors |
| Y. Serrestou, V. Beroulle, C. Robach |
How to Improve a Set of Design Validation Data by Using Mutation-based Test |
| J. Kadlec, M. Daněk |
Design and Verification Methodology for Reconfigurable Designs in Atmel FPSLIC |
| G. Bognár, G. Horváth, Z. Szűcs, V. Székely |
Die Attach Quality Testing by Fully Contact-less Measurement Method |
| T. Martínek, J. Kořenek, O. Fučík, M. Lexa |
A Flexible Technique for the Automatic Design of Aproximate String Matching Architectures |
| L. Sekanina, L. Stareček, Z. Kotásek |
Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules |
| H. Lampinen, P. Perälä, O. Vainio |
Design of a Scalable Asynchronous Dataflow Processor |
| G. Zhang, R. Farrell |
Embedded Built-In-Test Detection Circuit for Radio Frequency Systems and Circuits |
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| • 16:50 - 17:50 |
Student Session I
| J. Škarvada |
Test Scheduling for SoC under Power Constraints |
| J. G. Lomsdalen, R. Jensen, Y. Berg |
Self-refreshing Multiple Valued Memory |
| J. Bucek, R. Lorencz |
Comparing Subtraction-Free and Traditional AMI |
| P. Kubalík, R. Dobiáš, H. Kubátová |
Dependability Computation for Fault Tolerant Reconfigurable Duplex System |
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| • 17:50 - 18:50 |
Session IV
- Analog Design
| S.-C. Hsia, W.-C. Lee |
A New 6-bit Flash A/D Converter Using Novel Two-Step Structure |
| O. Šubrt, P. Martínek |
A Novel Design Evaluation Concept Applied to Switched-Current Algorithmic A/D Converters |
| Y. Joannon, V. Beroulle, R. Khouri, C. Robach, S. Tedjini, J.-L. Carbonero |
Behavioral Modeling of WCDMA Transceiver with VHDL-AMS Language |
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| • 19:00 - 21:00 |
Welcome Party
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THURSDAY, April 20 show/hide thursday
| • 08:30 - 09:10 |
Jaume Segura, University Illes Balears, Spain
- Keynote Presentation
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| • 09:10 - 10:30 |
Session V
- Analog and Mixed-Signal Test
| M. J. Barragan, D. Vazquez, A. Rueda |
A Sinewave Analyzer for Mixed-Signal BIST Applications in a 0.35um Technology |
| L. Balado, E. Lupon, L. García, R. Rodríguez-Montanés, J. Figueras |
Lissajous Based Mixed-Signal Testing for N-Observable Signals |
| P. Malošek, V. Stopjaková |
PCA Data Preprocessing for Neural Network-based Detection of Parametric Defects in Analog IC |
| S. Vock, U. Flogaus, H. M. von Staudt |
Productivity and Code Quality Improvement of Mixed-Signal Test Software by Applying Software Engineering Methods |
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| • 10:30 - 11:30 |
Coffee break + Poster Session II
| R. Leveugle, V. Maingot |
On the Use of Information Redundancy When Designing Secure Chips |
| R. Elbaz, L. Torres, G. Sassatelli, P. Guillemin, M. Bardouillet |
PE-ICE: Parallelized Encryption and Integrity Checking Engine |
| M. Novotný, J. Schmidt |
Normal Basis Multipliers of General Digit Width Applicable in Elliptic Curve Cryptography |
| M. Abbas, M. Ikeda, K. Asada |
Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow |
| A. Penttinen, R. Jastrzebski, R. Pöllänen, O. Pyrhönen |
Run-Time Debugging and Monitoring of FPGA Circuits Using Embedded Microprocessor |
| P. Geguang, H. Jifeng, Q. Zongyan |
An Optimal Lower-Bound Algorithm for the High-Level Synthesis Scheduling Problem |
| P. Dziurzanski, W. Bielecki, K. Trifunovic, M. Kleszczonek |
A System for Transforming an ANSI C Code with OpenMP Directives into a SystemC Description |
| E. Armengaud |
Low Level Bus Traffic Replay for the Test and Debugging of Time-Triggered Communication Systems |
| A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto |
A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs |
| R. Kothe, C. Galke, S. Schultke, H. Froeschke, S.Gaede, H. T. Vierhaus |
Hardware/Software Based Hierarchical Self Test for SoCs |
| J. Strnadel |
Power-Constrained, Sessionless SoC Test Scheduling Based on Exploration of I-Schedule State-Space |
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| • 11:30 - 12:30 |
Session VI
- Timing Issues in Design and Test
| X.-T. Tran, C. Robach, J. Durupt, V. Beroulle, F. Bertrand |
Design-for-Test of Asynchronous Networks-on-Chip |
| C. Metra, D. Rossi, M. Omana, J. M. Cazeaux, T. Mak |
Can Clock Faults be Detected Through Functional Test? |
| A. Fidalgo, G. Alves, J. Ferreira |
A Modified Debugging Infrastructure to Assist Real Time Fault Injection Campaigns |
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| • 12:30 - 13:30 |
Lunch
- Steering Committee Meeting
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| • 14:00 - 15:00 |
Yervant Zorian
- New Trends in Testing - Informal Session
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| • 15:30 - 18:30 |
Social event
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| • 19:30 - 24:00 |
Banquet
- Bethlehem Chapel
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FRIDAY, April 21 show/hide friday
| • 08:30 - 10:30 |
Session VII
- Fault Tolerance
| A. Krasniewski |
Low-Cost Concurrent Error Detection for FSMs Implemented Using Embedded Memory Blocks of FPGAs |
| H. Kariniemi, J. Nurmi |
Fault-Tolerant 2-D Mesh Network-on-Chip for Multi-Processor System-on-Chip |
| P. Vanhauwaert, R. Leveugle, P. Roche |
A Flexible SoPC-based Fault Injection Environment |
| G. I. Wirth, M. G. Vieira, E. H. Neto, F. G. L. Kastensmidt |
Generation and Propagation of Single Event Transients in CMOS Circuits |
| S. Biswas, P. Patra |
Concurrent Testing of Digital Circuits for Non-Classical Fault Models: Resistive Bridging Fault Model and n-Detect Test |
| R. Kothe, H. T. Vierhaus, T. Coym, W. Vermeiren, B. Straube |
Embedded Self Repair by Transistor and Gate Level Reconfiguration |
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| • 10:30 - 11:30 |
Coffee break + Poster Session III
| J. M. Fernandes, M. B. Santos, A. L. Oliveira, J. C. Teixeira |
Probabilistic Testability Analysis and DFT Methods at RTL |
| M. García-Valderas, M. Portela-García, C. López-Ongil, L Entrena-Arrontes |
An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories |
| S. V. Yarmolik, B. Sokol |
Optimal Memory Address Seeds for Pattern Sensitive Faults Detection |
| J. Jaroš, V. Dvořák |
Evolutionary Design of OAB and AAB Communication Schedules for Networking Systems on Chips |
| M. Ohlídal, J. Schwarz |
Collective Communication AAB for Regular and Irregular Topology Based on Prediction of Conflicts |
| H.-C. Chi, C.-M. Wu, S.-T. Wu |
A Switch Supporting Circuit and Packet Switching for On-Chip Networks |
| M. Šimlaštík, P. Malík, T. Pikula, M. Baláž |
FPGA Implementation of a Fast MDCT Algorithm |
| T. Garbolino, M. Kopec, K. Gucwa, A. Hlawiczka |
Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor |
| P. Bernardi, M. Grosso |
Test Considerations about the Structured ASIC Paradigm |
| M. Bucci, R. Luzzi |
A Leakage-based Random Bit Generator with On-line Fault Detection |
| V. Nagy, V. Stopjaková |
New Current Monitor Using Auto Zero Voltage Comparator for IDD Testing of Mixed-signal Circuits |
|
| • 11:30 - 13:00 |
Student Session II
| Z. Gajda, L. Sekanina |
A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming |
| Z. Mader, M. Jarkovsky |
SOC Diagnostic Design Using RESPIN Architecture |
| J. H. Choi, Y. D. Kim, Y. You |
Dynamic Decimal Adder Circuit Design |
| J. G. Lomsdalen, R. Jensen, Y. Berg |
Multiple Valued Counter |
| M. Šťáva, O. Novák |
HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic Reconfiguration |
| G. Perlaky, G. Mezősi, I. Zolomy |
Sensor Powering with Integrated MOS Compatible Solar Cell Array |
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| • 13:00 - 14:00 |
Lunch
|
| • 14:00 - 16:00 |
Session VIII
- Memory and Logic Test
| L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, M. Bastian |
March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit |
| G. Harutunyan, V. A. Vardanian, Y. Zorian |
Minimal March-Based Fault Location Algorithm with Partial Diagnosis for all Static Faults in Random Access Memories |
| P. Fišer, H. Kubátová |
Multiple-Vector Column-Matching BIST Design Method |
| L. Kafka, O. Novák |
FPGA-based Fault Simulator |
| F. Guerreiro, J. Semiao, A. Pierce, M.B. Santos, I. M. Teixeira, J. P. Teixeira |
Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage |
| T. Pečenka, Z. Kotásek, L. Sekanina |
FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties |
|
| • 16:00 |
Workshop closing
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| • 16:15 -17:15 |
Post Conference Programme
| A. Jutman (EST), Z. Plíva (CZ), E. Gramatová (SK) |
Hands-on Session for Demonstrating the Tools for Design and Test Developed in the REASON Project |
| W. Pleskacz, A. Jutman |
Study of Real CMOS Defects Using DefSim Educational Environment |
| E. Gramatova, Tomas Pikula |
Training Tools for DfT and BIST |
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